Publications of Benha University on Google Scholar: Formal semantics of VHDL timing constructs

Title:
Formal semantics of VHDL timing constructs
Authors: A Salem, D Borrione
Year: 1992
Keywords: Not Available
Journal/Conference: VHDL for Simulation, Synthesis and Formal Proofs of Hardware,
Volume: Not Available
Issue: Not Available
Pages: 195-206
Publisher: VHDL for Simulation, Synthesis and Formal Proofs of Hardware, 195-206
URL on Google: https://scholar.google.com.eg/citations?view_op=view_citation&hl=en&citation_for_view=QCRKlN4AAAAJ:zYLM7Y9cAGgC
Citations: 17
Paper Link: Not Available
Full paper Not Available