Publications of Benha University on Google Scholar: Formal verification of VHDL descriptions in the Prevail environment

Title:
Formal verification of VHDL descriptions in the Prevail environment
Authors: DD Borrione, LV Pierre, AM Salem
Year: 1992
Keywords: Not Available
Journal/Conference: IEEE Design & Test of Computers
Volume: 9
Issue: 2
Pages: 42-56
Publisher: IEEE Design & Test of Computers 9 (2), 42-56
URL on Google: https://scholar.google.com.eg/citations?view_op=view_citation&hl=en&citation_for_view=QCRKlN4AAAAJ:u5HHmVD_uO8C
Citations: 69
Paper Link: Not Available
Full paper Not Available