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Dr. Hatem Mohamed Mohamed Zakaria Radwan :: Publications:

High Data Rate Pipelined Adaptive Viterbi Decoder Implementation
Authors: Ahmed S. Mohamed, and Hatem M. Zakaria
Year: 2016
Keywords: Convolutional coding, Viterbi Decoder, Pipelining, Adaptive Viterbi algorithm
Journal: IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
Volume: 11
Issue: 3
Pages: pp. 109-115
Local/International: International
Paper Link:
Full paper Hatem Mohamed Mohamed Zakaria Radwan_Q110302109115.pdf
Supplementary materials Not Available

This paper presents a pipelined Adaptive Viterbi algorithm of rate ½ convolutional coding with a constraint length K = 3 which is designed in a reconfigurable hardware to take full advantage of algorithm parallelism, specialization and the throughput rate. In present work, the hardware implementation of the pipelined Adaptive Viterbi algorithm is performed using FPGA processor (Spartan-3AN starter Field Programmable Gate Array (FPGA) kit), and Model- Sim simulation results are performed to ensure that the implemented scheme satisfy the design specification. On the other hand, processing time, power consumption, and design capacity should be studied well for real time implementation.

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