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Ass. Lect. Eman Salem Abd Elaziz Salem :: Publications:

FPGA implementation of 1000base-x Ethernet physical layer core
Authors: EmanSalem; Abdelhalim Zekry; Hossam labeb; Radwa Tawfik
Year: 2018
Keywords: Giga Ethernet;virtex6 FPGA;PHY; PCS; PMA;8B/10B Coding; Synchronization; PISO; SIPO
Journal: International Journal of Engineering & Technology
Volume: 7
Issue: Not Available
Pages: 7
Publisher: Not Available
Local/International: International
Paper Link:
Full paper Eman Salem Abd Elaziz Salem_IJET-13469 eman _paper.pdf
Supplementary materials Not Available

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

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