This paper describes theimplementation of soft decision Viterbi channeldecoding algorithm using a digital signal processor. This was done through a computer simulation and also through using a dsp56f807evm digital signal processor (DSP). The dsp56f807evm DSP can achieve the performance of up to 40 million instructions per second (MIPS) at 80MHz core frequency and consequently has gained more and more popularity in many applications. Moreover, the implemented Viterbi decoder was tested againstan additive white Gaussian noise channel (AWGN) at different signal to noise ratios (S / N) and different convolutional code constraint lengths. |
