This work presents a hardware implementation of a Genetic Algorithm. Hardware
Genetic Operators are implemented in FPGA. Fitness evaluation, which is problem
dependent, is left for implementation as S/W module or problem specific hardware
design. This allowed a re-configurable general-purpose design, which is customized by
application specific population generation and fitness evaluation solution. A 16 site
Random Number Generator module is implemented in VHDL based on Hybrid Cellular
Automata (CA). Selection, Crossover, and Mutation Operators are implemented as
systolic architecture. For preserving locality & modularity of systolic arrays we separate
selection array implementation from the crossover and mutation operators. The
chromosomes are fed serially to allow variable length chromosomes. The Genetic
Engine is targeted a Xilinx Vertex XC2V2000-5 device using Xilinx Foundation
Environment. The simulation is carried out using ModelSim. |
