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Dr. Radwa Mohamed Tawfeek Awais :: Publications:

Title:
FAULT TOLERANT COMPUTING ARCHITECTURES. APPLICATION TO MEMORY SYSTEM ORGANIZATIONS.
Authors: Radwa M. Tawfeek
Year: 2007
Keywords: Fault Tolerance
Journal: Not Available
Volume: Not Available
Issue: Not Available
Pages: Not Available
Publisher: Not Available
Local/International: Local
Paper Link: Not Available
Full paper Radwa Mohamed Tawfeek Awais_RTMSc_THesis03_18_2007.pdf
Supplementary materials Not Available
Abstract:

The dramatic increase in the use of computers has been accompanied by a need for fault-tolerant computing which is the ability to make the system to work in its specified operation in case of the presence of error. This requirement can be seen in the real-time control of air traffic systems, nuclear power facilities, and medical life-support units, where faulty outputs or brief system failures could threaten life. Likewise, unmanned satellites and deep-space probes require maintenance-free computers. This need extends to virtually every non-disposable computer product, due to the soaring cost of computer servicing. In the same time, quadrupling single-chip memory storage every two years has required a comparable increase in memory reliability. Since more than half of all computer failures may be caused by faults in its random-access memory, improved performance requires increasing the time between failures in such devices. This increase should not significantly reduce memory-access speed, however, since writing to and reading from memory usually make up the slowest CPU task. The main techniques for detecting/correcting errors in memory are replication, reconfiguration, and coding. This Thesis presents the use of coding technique in order to detectcorrect errors in memory. Our focus is especially on semiconductor RAM. We used a (12,8) code and many arrangements of a (16, 8) quassi-cyclic code as an example for codes that can correct and detect single and double errors, triple adjacent errors and more. The thesis presents a new way for encoding/decoding the cyclic code. The theoretical study and simulation analysis for this new coding method is presented. Experiments design and results analysis is presented with the comparison of our new coding method for cyclic codes and different coding. The used coding method has the advantage of encoding and decoding the codewords in parallel instead of using the serial method. Moreover, the comparison with other coding methods is also presented to illustrate the ability of the new coding method to detection and correction of errors.

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