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Dr. Radwa Mohamed Tawfeek Awais :: Publications:

Title:
FPGA implementation of 1000base-x Ethernet physical layer core
Authors: E.S. Abdulaziz, A.Zekry, H.L. Zyed, R.M. Tawfeek
Year: 2018
Keywords: Giga Ethernet;virtex6 FPGA;PHY; PCS; PMA;8B/10B Coding; Synchronization; PISO; SIPO.
Journal: International Journal of Engineering & Technology
Volume: 7
Issue: 4
Pages: 2106-2112
Publisher: Not Available
Local/International: International
Paper Link: Not Available
Full paper Radwa Mohamed Tawfeek Awais_IJET-13469zekryemanrdwa.pdf
Supplementary materials Not Available
Abstract:

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

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