This paper presents ASIC (application specific integrated circuit) design and implementation of a high- Gigabit Ethernet (GE) transceiver with Forward Error Correction (FEC) layer utilizing Reed Solomon (RS) (255, 239) code. We designed 25 GE to provide a simpler and more cost-efficient path to future Ethernet speeds, including 50 Gbps, 100 Gbps, and beyond. Until recently, a majority of available 100 GbE implementations used ten lanes of 10 GE. But utilizing 4-lanes (425 G) is more economical. We also improved the design by insert FEC devices to provide error correction ability for optical communication system. RS (255, 239) CODEC (encoder/decoder) architecture was designed in parallel to be suitable for high-speed fiber-optic system. The proposed channel consists of 8 RS COCEC in parallel. Parallelizing and pipelining allow data to be transmitted at high fiber-optical rates and received at correspondingly high rates with minimal latency. The overall system was implemented by 45 nm CMOS standard cell technology of ten layers with standard cells in a supply voltage 1.1 V. In this design, at most 8 bytes errors for each data frame (255 Bytes) under the demanded working frequency 25 GHz can be detected and corrected. The fully VHDL codes for a complete system were synthesized by Synopsys design compiler based on NCSU 45 nm CMOS technology. Electronic Design Automation (EDA) tools are used for simulation, synthesis, physical implementation and errors check. The implementa-tion results obtained are exhibited during this paper. It shows that the designed structure has merits such as high efficiency and low power consumption ensuring good coding performance than previous designs. |
