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Dr. Radwa Mohamed Tawfeek Awais :: Publications:

Title:
VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier
Authors: Radwa M. Tawfeek ; Marwa A. Elmenyawi
Year: 2022
Keywords: 8x8 Multiplier; 16x16 Multiplier; Booth Multiplier; Modified Radix-4 Booth; Pipeline Multiplier; Zero Skip
Journal: International Journal of Electronics
Volume: Not Available
Issue: Not Available
Pages: Not Available
Publisher: Taylor & Francis
Local/International: International
Paper Link:
Full paper Not Available
Supplementary materials Not Available
Abstract:

Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction

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